A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling

Digital s y s t e m s design and verif ication becomes m o r e dijgicult a s the s ize of t he s y s t e m grows. T o solve th,is problem, m a n y CAD tools have been developed, including s imu la t ion . However , as s y s t e m s increase in size and complexi ty , s imu la t ing the s y s t e m becomes v e r y costly, both in t i m e and space. For m o s t cases tha t u s e s imu la t ion , on ly a subset of t he total possible s imu la t ion pa t t e rns i s used f o r design verif ication. T h i s paper describes a s i m u l a t i o n tool wh ich applies effective methodologies s u c h as: error compression and sampling, f o r reducing s imu la t ion t i m e and resources. T h e s e me thods sa t i s f y confidence level expectations f o r design verification, u s ing ei ther reduced design errors or reduced t e s t sets .